1. Field of the Invention
The present invention relates to a field of information processing adapted to processing image signals. More particularly, the present invention relates to an image operating processing apparatus having a function of using an image memory efficiently, and capable of executing a specific operation processing with high efficiency.
2. Description of the Background Art
Referring to FIG. 1, a data driven image operation processor 21 which is an example of a conventional image operation processing apparatus includes input ports IA and IB connected to data transmission paths 27 and 28, respectively, and output ports OA and OB connected to data transmission paths 29 and 30, respectively. The data driven image operation processor 21 further includes an output port OV and an input port IV connected to an image memory section 31 through data transmission paths 24 and 25, respectively.
Image memory unit 31 includes a memory interface 22 connected to data transmission paths 24 and 25, and an image memory 23 connected to memory interface 22 through a memory access control line 26.
Data driven image operation processor 21 time sequentially receives a signal input packet from data transmission path 27 or 28 through input port IA or IB. The signal input packet has a generation number allotted in accordance with time order of input. Packet format will be described later.
Data driven image operation processor 21 stores a pre-set content of processing or operation (data driven program), and processing proceeds in accordance with the set content. Data driven image operation processor 21 outputs an access request to image memory 23 from output port OV. Access request includes reference, update or the like of the content in image memory 23. Upon reception of the access request from data transmission path 24, memory interface 22 accesses image memory 23 through memory access control line 26. After accessing, memory interface 22 returns a result through data transmission path 25 and input port IV to data driven image operation processor 21.
After completion of the processing of the signal input packet, data driven image operation processor 21 outputs a signal output packet from output port OA or OB to data transmission path 29 or 30.
Referring to FIG. 2, a data packet 36 input to memory interface 22 through data transmission path 24 includes an instruction code 70, a generation number 72, first data 74, second data 76, a processor number 78 and an entry number 80.
Instruction code 70 indicates content of processing on image memory 23. For example, it indicates reference or updating of the content of image memory 23.
Generation number 72 is an identifier allotted in accordance with the order of input time sequence, at the time of input from data transmission path 27 or 28 to data driven image operation processor 21. Generation number 72 is utilized for matching of data at data driven image operation processor 21. Meanwhile, generation number 72 also has a meaning of an address for memory interface 22, when accessing image memory 23. A technique on which the present invention is based is disclosed in Japanese Patent Laying-Open No. 5-274213. In the technique disclosed in this laid-open application, the generation number is subjected to address modification (offset modification) using the first data 74 or the second data 76, and an address for accessing the image memory 23 is determined based on the address modified generation number. In the disclosure of this application, generation number 72 (24 bits) is divided into two, 12 bits by 12 bits, in accordance with initialization of data driven image operation processor 21. Operation proceeds assuming that the upper 12 bits represent position of a line on an image plane (that is, position in Y direction) and the lower 12 bits represent pixel information of the image plane (that is, position in X direction).
First and second data 74 and 76 are both data having meaning thereof changed in accordance with the content of instruction code 70. When instruction code 70 represents updating of image memory, for example, first data 74 represents data to be written to image memory 23. At this time, the second data 76 is meaningless. When instruction code 70 represents reference to image memory 23, both first and second data 74 and 76 are meaningless.
The processor number is a number unique to the processor to which the data packet is to be applied. When a data packet is received, the image operation processor determines whether the processor number 78 matches the processor number of itself, and if the number matches, the processor processes the data packet. If not, the processor outputs the data packet from either one of the output ports, to that processor which has the corresponding processor number.
Entry number 80 is information associated with the input packet.
In this example, data packets on data transmission paths 25, 27, 28, 29 and 30 each have the same structure as that shown in FIG. 2. However, data in each field may differ slightly. For example, in the data packet on data transmission path 25, instruction code 70 and generation number 72 are the same as the instruction code and the generation number of the input data packet applied to memory interface 22. A result of accessing to image memory 23 in accordance with instruction code 70 is stored in the first data 74. Entry number 80 is used for fetching an instruction or the like to be executed next, after an execution of the instruction. Entry number 80 corresponds to a program counter in a Von Neumann type processor. The second data 76 is, at present, meaningless.
The signal input packets are input time sequentially through input port IA or IB to data driven image operation processor 21. Data driven image operation processor 21 performs digital filtering or the like on the signal input packets. Results of processing by data driven image operation processor 21 may be written to image memory 23.
When the result of processing by data driven image operation processor 21 is written to image memory 23 as mentioned above, sometimes that the address modified generation number of the packet is thinned out by an execution program. As a result, sometimes data are stored sparsely in image memory 23, as shown in FIG. 3. The example shown in FIG. 3 corresponds to thinning out of data for displaying image data having 800.times.1024 pixels on a monitor having display resolution of 400.times.512 pixels after image processing, as shown in FIG. 4, for example. In the example shown in FIG. 4, it is necessary to maintain data of high resolution for data processing itself and satisfactory image processing is impossible if the resolution is lowered from the start. Here, data processing is performed with high resolution, and only the display of the image is given with low resolution. The data necessary for display are those of even-numbered addresses both in X and Y directions, that is, every other pixel. At this time, the state of data storage in image memory 23 is as shown in FIG. 3.
However, in this case, as can be readily seen from FIG. 3, the efficiency of use of image memory 23 is low. Memory address areas corresponding to the odd-numbered addresses are not used. In the example shown in FIG. 3, efficiency of use is 1/4, that is, 3/4 of the entire areas are not used. When a large amount of data is to be processed, such inefficient use of the memory should be avoided. Therefore, when it is known in advance that the data would be stored sparsely as shown in FIG. 3, it is preferred to use an image operation processor which has a function of improving efficiency of use of the memory in some way.
Further, the conventional data driven image operation processor has a problem that certain types of operations cannot be executed efficiently. It is especially problematic when an operation, typically an accumulation (summation) is performed on mutually adjacent plurality of data before writing the data to image memory 23 and the result of the operation is to be written to a prescribed address. In that case, the conventional data driven image operation processor processes in accordance with a flow graph of FIG. 5. In the example shown in FIG. 5, the generation number is divided into three. These divided pieces correspond to a field number, a line number and a pixel number of the image, for example. In FIG. 5, the generation number is depicted divided into three, at an upper left side of each node.
FIG. 5 is a flow graph of a process in which data corresponding to continuous 8 addresses are accumulated. The operation $ DR represents writing of data of the packet to an address which is designated by a modification value of the instruction and the generation number of the packet. The operation $ DNADD 0 represents an operation in which data is read from an address designated by the modification value of the instruction and the generation number of the packet, the read data is added to data in the data packet, and the result is taken as the data in the packet. Conventionally, it has been necessary to read data of respective addresses one by one and add the read data in order, as shown in FIG. 5, and finally to write the data at a desired address (not shown in FIG. 5). The longer the flow graph, the larger the amount of operation and the slower the speed of processing. It is desired that the flow graph of FIG. 5 is made shorter.